library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.faw_types.all;

entity TCP_ShiftRegister is
        Port ( 
                          clk_tcpsr : in  STD_LOGIC;
           data_in_tcpsr : in  STD_LOGIC_VECTOR (7 downto 0);
                          we_tcpsr : in STD_LOGIC;
           oe_tcpsr : in  STD_LOGIC_VECTOR (N_DISPARITY-1 downto 0);
           sclear_tcpsr : in  STD_LOGIC;
                          data_out_tcpsr : out  TCPSR_SR_DATA_BUS
                          );
end TCP_ShiftRegister;

architecture Behavioral of TCP_ShiftRegister is

component SR_CELL is
                port(
                        d : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                        clk : IN STD_LOGIC;
                        sclr : IN STD_LOGIC;
                        q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
                );
        end component;

        SIGNAL INTERNAL_BUS : TCPSR_SR_DATA_BUS;
        signal internal_clock : std_logic;

begin

        ShiftRegisterFirstCell : SR_CELL
                port map(
                        clk=>internal_clock,
                        d=>data_in_tcpsr,
                        q=>INTERNAL_BUS(0),
                        sclr=>sclear_tcpsr
                );
        
        ShiftRegisterInternal : for i in 1 to N_DISPARITY-1 generate
                comp: SR_CELL
                port map(
                        clk=>internal_clock,
                        d=>INTERNAL_BUS(i-1),
                        q=>INTERNAL_BUS(i),
                        sclr=>sclear_tcpsr
                );
        end generate ShiftRegisterInternal;

		internal_clock<=clk_tcpsr and we_tcpsr;
        processo:process(clk_tcpsr)
                
        variable DATA_OUT: TCPSR_SR_DATA_BUS;
                begin
                        if (clk_tcpsr'event and clk_tcpsr='1') then
                               -- if(we_tcpsr='1')then
                                 --       internal_clock<=clk_tcpsr;
                                --else
                                  --      internal_clock<='0';
                               -- end if;
                                
                                for i in 0 to N_DISPARITY-1 loop
                                        if(oe_tcpsr(i)='1')then
                                                DATA_OUT(i):=INTERNAL_BUS(i);
                                        else
                                                DATA_OUT(i):= (others=>'Z');
                                        end if;
                                end loop;       
                                data_out_tcpsr<=DATA_OUT;
                        end if;
                        
--                        if (clk_tcpsr_false'event and clk_tcpsr_false='1') then
--                                --if(we_tcpsr='1')then
--                                        internal_clock<='0';            
--                                --end if;
--
--                        end if;
                end process;
                
end Behavioral;
